UC Irvine

Graphics Processing Units (GPUs) are specialized hardware that was originally created to accelerate computer graphics and image processing. However, their highly parallel structure and their low costs per GFlop per Watt make them attractive as energy efficient performing architectures that accelerate other computationally-intensive scientific tasks.

NVIDIA is the market leader for GPUs. To protect its market leadership position, NVIDIA does not disclose its real assembly (ELF) Instruction Set Architectures (ISAs), keeps the compiler code closed, and does not disclose many of its low level GPU architectural features and machine behaviors. Optimization processes therefore become very time consuming and involves trials and errors.

In this thesis we design and implement a set of autonomic tools to reverse engineer the ELF ISAs and design and implement another set of autonomic tools to discover and quantify the GPU low level architectural features and machine behaviors. We also show that, even when implementing kernels using NVIDIA virtual assembly (PTX), more than 40% of the total performance is lost. This is compared to implementing the same kernels using the ELF ISAs and exploiting the insight yielded from the discovery, understanding, and quantification of the GPU low level architectural features and machine behaviors.