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Limited exception modeling and its use in presynthesis optimizations

Abstract

In behavioral descriptions, statements that allow limited control jumps, such as Verilog disable statments on named blocks, are often used for describing system behavior in presence of exceptions. In this paper, we extend the Timed Decision Tables (TDT), a tabular model of behavioral descriptions, to represent more general control structures including exceptions. We introduce the notion of action sharing that allows us to reduce resource requirements using existing high-level synthesis tools on descriptions with control exceptions. We present presynthesis algorithms that works on the extended TDT model and algorithms to perform action sharing in TDT models. Our experiments on well-known HardwareC benchmarks show size reduction resulting from sharing actions in the input behavioral descriptions.

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