UC Berkeley

In the past few decades, wireless connectivity has grown from an expensive luxury to an integral component of everyday life, creating a need for wireless systems that can satisfy exponentially growing demand for data in an energy- and cost-efficient manner. New techniques such as digital beamforming can utilize spatial diversity to support multiple users with arrays of radio elements, but the required performance of these elements varies with array size. Additionally, while conventional single-element radios are typically designed to meet stringent performance requirements outlined in wireless standards, peak performance is rarely required. Adaptive wireless receivers that configure performance to suit a system’s needs may therefore serve as building blocks for energy-efficient wireless platforms, and enhanced digital processing capabilities afforded by CMOS technology scaling can help realize fully integrated smart wireless systems. However, while computation improvements due to process scaling have driven the adoption of smart devices, complex design rules and lower supply voltages often make it difficult to construct high-performance analog circuits such as wireless receivers in advanced process nodes. To that end, this dissertation discusses the design and implementation of analog-to-digital interface circuits for receivers that are both configurable and well-suited to implementation in scaled nodes optimized for digital performance. It first explores circuit-level techniques for constructing resolution-configurable receivers from scalable elements, and then discusses an alternative receiver design that can integrate scalability at the architecture level.

To explore how circuit-level design techniques can enable configurability, this dissertation first discusses the design of a resolution-scalable successive approximation (SAR) analogto-digital converter (ADC) for wireless receiver applications. The converter is built with a scalable capacitive digital-to-analog converter (DAC), comparator, and tunable switching algorithm to trade power for resolution. The 80 MS/s prototype converter implemented in a general purpose 65nm CMOS process consumes 0.4-0.8 mW and provides 7.0-9.1 effective bits of resolution in a 10 MHz signal bandwidth. It is integrated with a power-scalable receiver to demonstrate its suitability for wireless systems. By trading noise for power consumption, this receiver can serve as a building block for energy efficient digital beamforming arrays.

Finally, this thesis demonstrates architectural techniques for affording configurability by discussing the design and implementation of a reconfigurable, digital-intensive RF-todigital converter. The proposed receiver uses a SAR ADC with integrated discrete-time filtering to provide high linearity and a voltage-controlled oscillator (VCO) based ADC to improve sensitivity. By replacing the high-performance active amplifiers and filters used in conventional receivers with an ADC constructed from digital building blocks, the 16nm CMOS FinFET prototype can leverage the benefits of technology scaling. In low-power mode, the 0.7-1.9 GHz receiver is configured as a VCO-based design drawing 9-16 mW and providing -82 dBm sensitivity in a 10 MHz bandwidth. In blocker-tolerant mode, the SAR ADC can be enabled to obtain 60 dB SNDR and an in-band IIP3 of +16 dBm. The prototype achieves performance comparable to state-of-the-art RF-to-digital converters using an easily configurable digital-intensive design. Overall, both configurability techniques discussed in this dissertation are promising means of leveraging the advantages of CMOS scaling to enable future digitally adaptive wireless systems.