UC Berkeley

Recent advancement in brain-machine-interface (BMI) technology has made tremendous impact on both clinical treatment and neuroscience research. It enables neural scientists to record and study signals fired by an individual neuron. To decode simple actions such as open and close a hand or rudimentary movements of an arm, signals from close to a hundred neurons must be examined [Hochberg06]. The large amount of collected neural data must be transmitted out of the skull to an external processer to translate into action or to be analyzed. To minimize the risk of infection to the patients, wireless data transmission is the preferred option. A next-generation 1024-channel implanted neural recorder that uses 20KS/s 8b Analog-to-Digital Converter (ADC) to capture neural signals can generate up to 164Mb/s data, which imposes a stringent requirement on the communication throughput of the implanted wireless transmitter (TX). In addition, TX power consumption must be kept as low as possible for longer battery life or safe wireless power delivery, while the power consumption of the external receiver (RX) chip outside the skull can be relaxed. The current state-of-the-art implantable transmitters that use backscattering, pulse harmonic modulation (PHM), or ultra-wide-band (UWB) communication suffer either from limited throughput or low TX energy efficiency. Although other techniques such as ultrasound have the potential to achieve ultra-low power, they suffer from low data-rate (tens to hundreds of Kb/s) and severe loss through the skull bone. To overcome these issues, inductive coupling technique is adopted in this work. The proposed transmitter only consists of an inductor driver, which significantly simplifies the TX architecture and lowers power. Inter-symbol-interference (ISI) caused by the ringing of the coupled inductors is alleviated by series de-Q resistors. To further reduce power, the entire TX uses a single 0.5V supply. To generate low jitter TX clock under such low supply and stringent power requirement, injection locked phase-locked loop (PLL) with fully-digital background frequency tracking and spur suppression is utilized. To demonstrate the proposed architecture, a 200Mb/s transceiver is implemented in 65nm CMOS process. The 10mmX10mm coupled inductors are fabricated on standard 2-layer FR-4 PCBs, on which the chips are directly bonded. The prototype achieves 5e-11 bit-error-rate (BER) over 11mm-thick scalp and skull bone of an 8-week primordial piglet and less than 1e-12 BER over 11mm air gap. The TX PLL rms jitter is 59ps. Including PLL, the entire TX chip consumes 300uW, achieving 1.5pJ/b energy efficiency. The power consumption of the external RX chip is 37.2mW. To the author’s best knowledge, the prototype achieves the highest data-rate and lowest BER among all cm-range wireless transceivers for biomedical implant applications.