UC San Diego

The semiconductor industry continues to pursue the scaling of three-dimensional integrated circuits (ICs), achieved by reducing the size of devices and interconnects. This downsizing of IC components enhances performance and reduces power consumption by shortening interconnect lengths. However, as ICs scale down to nanometer dimensions, issues related to patterning mask misalignment and interconnect misalignment become prominent. Mask misalignment can cause mask pattern transfer defects and pattern transfer in low resolution. In order to address the problem of mask misalignment, Bencher et al. introduced the concept of self-aligned chemical vapor deposition (CVD), also known as area-selective CVD 1. This method has since evolved into a self-aligned quadruple patterning technique in recent years 2. The core idea involves selectively depositing a spacer or etch stop material onto the preferred locations within a pre-etched structure, effectively halving the pitch of the integrated circuit. Interconnect misalignment can result in undesired short-circuits and capacitive coupling between vias and metal lines. Chen et al. have shown that the issue of misalignment can be effectively resolved using the dielectric on dielectric (DOD) deposition method 3. This process requires selectively deposition of a dielectric buffer layer onto the existing dielectric, giving it preference over the metal component. The selective dielectric layer effectively increases the separation between misaligned vias and the adjacent metal lines, thereby enhancing performance in terms of reducing short-circuits, capacitive coupling, and mitigating time-dependent dielectric breakdown (TDDB) 3.In Chapter 1, this work is an extension of our prior research efforts. Selective TiO2/Al2O3 and HfO2/Al2O3 pulsed CVD were investigated on Si, SiO2 and SiCOH substrates, where SiCOH is a methyl terminated Si substrate provided by Applied Materials. For TiO2/Al2O3 nanolaminate, Titanium(IV) Isopropoxide and Trimethylaluminum (TMA) were used as precursors. For HfO2/Al2O3 nanolaminate, Hafnium(IV) tert-Butoxide and TMA were used as precursors. In this study, TMA was discovered to improve the selectivity of both nanolaminates on Si, SiO2 in preference to SiCOH. Dielectric on metal was also achieved on the copper region of a nanoscale copper/SiCOH patterned sample. These selective nanolaminates can be a strong candidate for the spacer or etch stop layer in self-aligned double or quadruple patterning method. In Chapter 2, with the help of aniline, TiO2, HfO2, and Al2O3 were able to selectively deposit on SiO2 substrate in preference to W substrate. Titanium(IV) Isopropoxide, Hafnium(IV) tert-Butoxide, and Aluminum-tri-sec-butoxide were used as the respective precursors. Selective deposition at the nanoscale was also demonstrated on a patterned W/SiO2 sample with a pitch size of 55 nanometers. The deposited thin films exhibit a consistent smoothness and uniformity across the entire sample. The selection between HfO2 and Al2O3 processes for dielectric on dielectric (DOD) can be customized based on the intended application and the specific target dielectric constant (k value). Chapter 3 describes selective nanolaminate pulsed CVD using Aluminum-tri-sec-butoxide (ATSB) together with Tris(tert-butoxy) Silanol (TBS) to achieve AlOx/SiOx nanolaminate DOD on SiO2 substrate in preference to W substrate. 3 nanometer selectivity was achieved with 50 pulses ATSB at 330°C and 60s TBS at 200°C per supercycle. By following this supercycle procedure, a 28-nanometer low-k nanolaminate were obtained after 14 supercycles, resulting in a dielectric constant of 3.3. With 25 pulses ATSB at 330°C and 60s TBS at 200°C per supercycle, a low-k nanolaminate with a dielectric constant of 2.5 was achieved. 1. Bencher, C.; Chen, Y.; Dai, H.; Montgomery, W.; Huli, L. 22nm Half-Pitch Patterning by CVD Spacer Self Alignment Double Patterning (SADP). Opt. Microlithogr. XXI 2008, 6924 (March 2008), 69244E. https://doi.org/10.1117/12.772953. 2. Juncker, A.; Clark, W.; Vincent, B.; Franke, J.-H.; Halder, S.; Lazzarino, F.; Murdoch, G. Self-Aligned Block and Fully Self-Aligned via for IN5 Metal 2 Self-Aligned Quadruple Patterning. SPIE Adv. Lithogr. 2018, No. March 2018, 29. https://doi.org/10.1117/12.2298761. 3. Chen, H.; Wu, Y.; Huang, H.; Tsai, C.; Lee, S.; Lee, C.; Wei, T.; Yao, H.; Wang, Y.; Liao, C.; Chang, H.; Lu, C.; Shue, W.; Cao, M. Fully Self-Aligned Via Integration for Interconnect Scaling Beyond 3nm Node. 2021 IEEE International Electron Devices Meeting (IEDM), 2021, pp. 22.1.1-22.1.4, doi: 10.1109/IEDM19574.2021.9720600.