UC Riverside

In the next few years, the 5th generation of mobile network employing the massive multiple input multiple output (MIMO), beam-forming, mm-wave frequency bands and carrier aggregation techniques will further increase the data rate to enrich the growing of mobile devices at the price of more complex multi-band, multi-frequency front end module (FEM). As an indispensable part of radio-frequency front end (RFFE), antenna switch circuit needs more restrict performance not only the basic insertion loss, isolation and power handling capability, but the requirements from higher data rate, low interference and better reliability of 5G application.

To achieve those additional requirements for 5G RF switch with 45nm silicon-on-insulator (SOI) CMOS technology, this dissertation presents a novel multi-bands switch array structure to analysis the interference between switches in a single chip. The comprehensive study of switch array reveals that existing noise isolation techniques are insufficient and calls for novel in-die interference elimination. To reduce this in-die crosstalk, an above-silicon through back-end-of-line (BEOL) metal wall is developed as a practical solution with about 18.5dB (~98.6%) suppression. To reach a higher data rate with available frequency bands, millimeter wave (mm-wave) switches (28GHz/38GHz) has been demonstrated with the consideration of reliability issue of electrostatic discharge (ESD) which will introduce severe parasitic effects under this frequency level and degrade the performance of RFICs. The insertion loss and isolation together with ESD protection capability have been compared which shows the importance of ESD-RFIC co-design. Considering the necessity of accurate estimation for ESD performance, a novel methodology for both human body model (HBM) and charged device model (CDM) ESD protections using combined TCAD simulation and TLP/VFTLP measurements is depicted. To improve the accuracy of parasitic capacitance extraction, this dissertation introduces an enhanced de-embedded method with the help of HFSS simulation which reduces one third of the testchip size and gives a better reference for co-design.