UC Santa Cruz

This thesis describes Santa Cruz Instruction Processor with Scoreboarding (SCIPS) which is an aggressive 64-bit 2-way superscalar processor with Scoreboard logic implementing

the SCCORE ISA designed in System Verilog.

The SCIPS consists of a Scoreboard unit - which serves as the control section to stream instructions to the Execute unit resolving potential hazards; the Execute unit which comprises of 5 different functional units, including a skewed associative data cache.

SCIPS is a flexible pipelined design owing to the Stage implementation which tolerates any latency in the pipeline, allowing SCIPS to be re-pipelined at will, helping in significant power savings besides performance improvements.