UC Berkeley

The explosive development of various computation and communication platforms has demanded the per-pin I/O bandwidth of wireline links to increase at a commensurate rate, with projections to reach 60+Gb/s in less than 10 years. However, unlike the data-rate requirement, the power consumption of these links cannot increase, making improvements in the energy-efficiency of high-speed architectures and circuits crucial. In particular, equalization circuits such as feed-forward equalizers (FFE) and decision-feedback equalizers (DFE) are faced with the burden of compensating higher channel losses while running at faster speeds - all without allowing any increase in power consumption.

To address these challenges, this thesis first presents a feed-forward equalizing transmitter that utilizes voltage-mode signaling along with a shunting branch technique to improve signaling power. Due to the linear mapping between the equalization strength and output impedance segmentation from this technique, the associated decoding logic can be greatly simplified, and, thus, digital power overhead can be substantially reduced. Regulator-based impedance tracking loops are utilized to reduce the parasitics on the high-speed digital path to further reduce the digital power. A 2-tap prototype based on this architecture was taped out in Fujitsu 65nm LP CMOS process and achieves an overall of efficiency of 1pJ/b when operating at 10Gb/s with 200mV differential output signal amplitude.

To enable energy-efficient DFEs at even higher speeds, this thesis will then describe means to reduce the latency of the circuits within the intrinsic feedback loop of such equalizers. Specifically, techniques such as merged latch and summer, optimized signaling swing, and dynamic latches are combined to enable a multi-tap closed-loop DFE architecture that is capable of running at 60+Gb/s. A 3-tap prototype chip was fabricated in TSMC 65nm GP CMOS process, achieving ~0.7pJ/b at 66Gb/s when cancelling a total inter-symbol interference of ~1.65x of the cursor amplitude. This design represents by far the fastest DFE demonstrated to date with energy efficiency of better than 1pJ/bit, and highlights that the adoption of such techniques may pave the way forward for continued electrical I/O data-rate scaling.

After the introduction of these equalization circuits, this thesis will present a holistic link evaluation framework that aims to achieve more accurate power and performance estimation of link architectures at the beginning of a link design phase. With a compact circuit modeling methodology, circuit power and noise can be explicitly expressed in terms of both technology and system parameters (e.g. equalization-related parameters) such that a link's overall power and bit-error-rate can be directly estimated. An evaluation example shows that using TSMC 65nm GP CMOS process, it is possible to achieve a 64Gb/s data communication speed over a 1m long coax cable-based platform, which aligns with the previous DFE experimental results and thus proves the potentials of using this framework to guide the continued wireline data-rate scaling.