UCLA

There has been growing demand for high performance nanochips due to the Fourth Industrial Revolution. However, semiconductor manufacturing leaders are struggling to meet the need due to the current challenges and requirements, such as displacement of vertically stacked architectures and stricter film quality. Despite leveraging revolutionary technology such as atomic layer deposition (ALD), the development of more advanced techniques are necessary to address these challenges. Recently, atomic layer etching, as a counterpart of ALD, and area-selective atomic layer deposition, as a bottom-up nanopatterning technique, have recently gained momentum due to their potential abilities to satisfy the stringent quality specification and assemble nanostructures in a self-aligned manner. Thus, in this dissertation, a series of in silico research using multiscale computational fluid dynamics modeling have been performed to provide comprehensive understandingand insight to industry with respect to operation and robust control in order to further miniaturize the dimension of chips and precisely stack 3D features on semiconductors.