UC Berkeley

The semiconductor industry has relied on accurate device models for analyzing, predicting and innovating integrated circuit design. Multi-gate MOSFET device architectures like FinFETs are beginning to replace their planar MOSFET counterparts at the 22nm technology node to enable continued technology scaling. Vertical cylindrical gate (CG) MOSFET are touted to replace planar MOSFETs as the memory device for DRAM and NAND Flash offering increased area density. New device architectures together with relentless scaling of MOSFETs for performance mean increased complexity and new device physics that need to be comprehended. This new understanding needs to be translated into device models for technology progress. Newer device models also require newer methodologies for model creation process and usage for circuit design.

In this thesis we develop a comprehensive compact SPICE model for a CG MOSFET. Relying on fundamental physics based electrostatics description (Poisson Equation) of the device analytic equations for terminal current and capacitance are derived forming the core model. Including all requisite real device effects we validate this model to both numerical simulations (TCAD) and hardware silicon data showing < 1% RMS error when the model is tuned to the data. For channel diameters < 20nm quantum mechanical confinement effects tend to dominate. The complex bias and geometry dependence of the inversion charge centroid is captured through a phenomenological model. This model helps accurate prediction of the reduction in gate capacitance of a CG MOSFET. This model was also extended to carrier confinement in thin channels such as the double gate FET or FinFET. The vertical CG MOSFET exhibits asymmetry w.r.t. source and drain. With the aid of TCAD we propose that non-uniform vertical channel doping and structural differences in the top and bottom (source/drain) junction regions as the major contributors to the asymmetric behavior. We then create a mathematical framework to capture these asymmetries in the compact model developed above. We validate this approach by showing excellent agreement to hardware silicon data from a high voltage vertical CG MOSFET technology. All these models have been incorporated in BSIM-CMG the first industry standard multi-gate MOSFET model. Despite including many complex physical effects the resultant model can be executed in the order of few 10's of secs (per operating point) enabling rapid very large scale integrated circuit design.

A compact SPICE model maintains a balance of predictive nature and flexibility with many sub-components describing various physics and tunable parameters in order to capture data from various sources accurately. This could quickly become unmanageable during a model creation process. For this we propose a RF model extraction procedure that does not require any additional sub-circuit elements and takes advantage of advances in parameter optimization tools available today in an efficient manner. We demonstrate this procedure on high frequency data from multiple planar MOSFET technologies discussing various use cases. Using BSIM6, a bulk planar MOSFET compact model the resultant procedure was able to capture silicon data even beyond the cut-off frequency of the MOSFET and predict various RF circuit design figure of merits with great accuracy.