UC Riverside

Several key attributes of a 3D integrated chip structure are analyzed in this chapter. Critical features related to the effect of the size of the substrate, heat sink, device layer, through silicon vias (TSVs), thermal interface material (TIM), and the pitch and arrangement of core processors and TSVs as well as variation of thermal conductivity and total heat dissipation and distribution of power within the device layers core processors are investigated in depth. The effect of variation of pertinent features of the 3D IC structure on thermal hotspots are established and the optimum route for its reduction is clarified. In addition, a revealing analysis of the effect of the number of layers in the 3D structure is presented. Furthermore, the features that have an insufficient effect on reduction of thermal hotspots are also established and discussed.