UCLA

With the data rate of peripheral serial I/O for PCs and mobile computing platforms continuing to scale to meet high-bandwidth applications, the conventional serial interfaces are more than more challenging to achieve high bandwidth (>10Gb/s per lane), high energy efficiency (<10pJ/bit) and low cost, especially on complicated channel conditions, such as multi-drop buses and low-cost connectors/cables.

Conventional equalization solutions are very power-hungry and there is no universal solution capable of handling all different channel conditions. In the dissertation, a multi-band signaling with channel response learning mechanism will be introduced and a cognitive serial interface system will be proposed. The cognitive multi-band scheme mitigates equalization requirement and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio and channel bandwidth.

A cognitive tri-band transmitter (TX) and receiver (RX) with a forwarded clock using multi-band signaling and high-order digital signal modulations are designed, implemented and measured for serial link applications. The cognitive serial interface system features learning an arbitrary channel response by sending a sweep of continuous wave, detecting power level at RX side, and then adapting modulation scheme, data bandwidth and carrier frequencies accordingly based on detected channel information. The supported modulation scheme ranges from NRZ/QPSK to PAM-16/256-QAM. The proposed highly reconfigurable transceiver architecture is capable of dealing with low-cost serial channels, such as low-cost connectors, cables or multi-drop buses (MDB) with deep and narrow notches in the frequency domain (e.g., 40 dB loss at notches). The adaptive multi-band scheme mitigates equalization requirements and enhances the energy efficiency by avoiding frequency notches and utilizing the maximum available signal-to-noise ratio (SNR) and channel bandwidth. The implemented cognitive serial interface prototype consumes 14.7 mW /15.2 mW power and occupies 0.016 /0.024 mm x mm on TX and RX side respectively. It achieves a maximum data rate of 16 Gb/s with forwarded clock through one differential pair and the most energy-efficient Figure of Merit (FoM) of 20.4 �W/Gb/s/dB for TX and 21.1 �W/Gb/s/dB, which is calculated based on power consumption of transmitting and receiving per Gb/s data and simultaneously overcoming per dB worst-case channel loss within the Nyquist frequency.