UCLA

In this dissertation, we examine the effect of four sources of circuit imperfections on the performance of analog-to-digital converters (ADCs), including sampling clock jitters, spurious sidebands, timing mismatches, and gain mismatches. These imperfections distort the sampled data and degrade the signal-to-noise ratio (SNR) of the ADCs. We develop signal models for the distortions and propose effective adaptive signal processing techniques to filter the sampled data and mitigate the spurious effects. Rather than remove the distortions by perfecting the circuitry, the proposed techniques focus on processing the sampled data by using adaptive DSP algorithms.

Analog circuit impairments create many distortions including I/Q imbalances, phase noise, frequency offsets, and sampling clock jitter. Timing jitters generally arise from noise in the clock generating crystal and phase-locked-loop (PLL). The jitters cause the ADCs to sample the input signals at non-uniform sampling times and introduce distortion that limits the signal fidelity and degrades the SNR. While the effects of jitter noise can be neglected at low frequencies, applications requiring enhanced performance at higher frequencies demand higher SNR from the sampling circuit. We first examine the effect of the clock jitter on the SNR of the sampled signal and subsequently propose compensation methods based on a signal injection structure for direct down-conversion architectures.

We also address the effect of non-ideal PLL circuitry on the quality of the sampled data. In a non-ideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used to generate the sampling clock, it injects the spurious tones into the sampled data. These distortions are harmful for wideband applications, such as spectrum sensing, since they affect the detection of vacant frequency bands. We again examine the distortion effect in some detail and propose techniques in the digital domain to clean the data and remove the PLL leakage effects. We study the performance of the proposed algorithms and compare it against the corresponding Cramer-Rao bound (CRB).

We further propose an adaptive frequency-domain structure to compensate the effect of timing and gain mismatches in time-interleaved ADCs. An M-channel time-interleaved ADC uses M ADCs to sample an input signal to obtain a larger effective sampling rate. However, in practice, combining ADCs introduces mismatches among the various ADC channels. In the proposed solution, the signal is split into multiple frequency bins and adaptation across the frequency channels is combined by means of an adaptive strategy. The construction is able to assign more or less weight to the various frequency channels depending on whether their estimates are more or less reliable in comparison to other channels.