UC Irvine

Multi-pixel passive imaging arrays are presently fabricated in expensive processes with low integration levels. Imaging arrays designed in inexpensive processes with higher levels of integration would result in cheaper larger arrays. The objective of this work is twofold: 1) to develop a highly integrated silicon-based passive imaging receiver integrating the entire receiver frontend from antenna to detector; and 2) to develop a highly scalable architecture for use in focal plane arrays of arbitrary dimensions, incorporating new features to address large-array issues while retaining the pixel density of conventional focal plane arrays. A new area-efficient beam-steerable imaging array receiver architecture suitable to integrated circuit realization up to sub-THz frequencies is presented. A direct-detection-based receiver array utilizing the proposed architecture is designed and implemented in an advanced 0.18µm BiCMOS process. The receiver chip achieves a peak measured coherent responsivity of 1,150MV/W, a measured incoherent responsivity of 1,000MV/W, a minimum NEP of 0.28fW/Hz^1/2 and a front-end 3-dB bandwidth from 87&ndash108GHz, while consuming 225mW per receiver element. The measured NETD of the SiGe receiver chip is 0.45K with a 20ms integration time. The proposed architecture uses a new concept of spatial-overlapping super-pixels which results in (1) improved SNR at the pixel level through a reduction of spillover losses, (2) partially correlated adjacent super-pixels, (3) a 2×2 window averaging function in the RF domain, (4) the ability to compensate for the systematic time delay and amplitude variations due to the off-focal-point effect for antennas away from the focal point, and (5) the ability to compensate for mutual coupling effects among the array elements.